1. Field of the Invention
The invention relates generally to a floating-point digital-to-analog converting system (called DAC hereafter), and more specifically to a floating-point DAC preferably applied to digital audio apparatuses such as compact disk players.
2. Prior Art
A floating-point DAC that converts digital data represented by 2's complement of 22-bits into an analog signal is constructed as shown in FIG. 1 (though FIG. 1 is a block diagram of an embodiment of the invention, it is also used here to illustrate the conventional apparatus). In FIG. 1, 1a designates a shift processor comprising input buffers all designated as 2, 2, . . . , a shift-number-detection circuit 3a, a digital-shift circuit 4, and an inverter 5. Digital input data of 22-bits I.sub.0 to I.sub.21 is applied to the digital-shift circuit 4 through the input buffers 2, 2, . . . The upper 7-bits I.sub.15 to I.sub.21 of the 22-bits, forming the exponent thereof, are supplied to the shift-number-detection circuit 3a which produces shift numbers S.sub.0 to S.sub.6 according to the exponent. The digital-shift circuit 4 produces 15-bit digital mantissa M.sub.0 to M.sub.14 by shifting the input data I.sub.0 to I.sub.20 by bit positions specified by one of the shift numbers S.sub.0 to S.sub.6. The inverter 5 inverts the most significant bit I.sub.21 of the input data and produces the reversed bit as the most significant bit M.sub.15 of the digital mantissa.
Numeral 6 designates a mantissa DAC 6 that converts the digital mantissa M.sub.0 to M.sub.15 to an analog mantissa. It comprises a buffer circuit 7 and R-2R ladder network 8. The buffer circuit 7 is provided with a pair of serially connected inverters for each bit which produces high or low voltage according to logic-1 or logic-0 of each bit of the digital mantissa M.sub.0 to M.sub.15. The R-2R ladder network 8 receives each bit of the digital mantissa, multiplies each bit by a specific weight, and sums the resulting products, thus producing an analog mantissa.
Numeral 9 designates an exponent DAC which produces analog output V.sub.OUT that corresponds to the input data I.sub.0 to I.sub.21, using the analog mantissa applied from the mantissa DAC 6 and the shift numbers S.sub.0 to S.sub.6 supplied from the shift-number-detection circuit 3a. It comprises a R-2R ladder network 10 and a switch circuit 11. The R-2R ladder network 10 multiplies the analog mantissa by weight specified by one of the shift numbers S.sub.0 to S.sub.6 and the reference voltage V.sub.MP. The switch circuit 11 consists of 7 switch elements, one of which turns on according to one of shift numbers S.sub.0 to S.sub.6 of logic-1.
In the construction mentioned above, the shift-number-detection circuit 3a determines the shift numbers S.sub.0 to S.sub.6, as shown in FIG. 2(a) and (b). Analog levels represented by digital notation as from +2097151 to -2097152 in FIG. 2(a), are divided into 2.sup.4 (=16) levels by every 6 dB interval, and the shift numbers S.sub.0 to S.sub.6 are determined as shown in FIG. 2(b). Specifically, when the absolute value of the analog level ranges from the maximum to 1/2 thereof, the shift number S.sub.0 is assigned; from 1/2 to 1/4, the shift number S.sub.1 is assigned; from 1/4 to 1/8, the shift number S.sub.2 is assigned, and so on. Each digital mantissa M.sub.0 to M.sub.14 is selected from the input data I.sub.0 to I.sub.20 according to the shift numbers S.sub.0 to S.sub.6 as shown in FIG. 2(a): solid arrows (.rarw..fwdarw.) in the input data table shown in FIG. 2(a) designate the range to be selected as a digital mantissa M.sub.0 to M.sub.14. Inspection of FIG. 2(a) shows that every time the analog level is halved, shift numbers S.sub.0 to S.sub.6 are changed, as well as the input data I.sub.0 to I.sub.20 to be selected as a mantissa is shifted. Furthermore, mantissa M.sub.15 is obtained as a reversed value of the input data I.sub.21.
FIG. 3(a) depicts the relationships between analog levels and the shift numbers S.sub.0 to S.sub.6. Each time the amplitude of the analog signal is halved (i.e., every 6 dB interval), one of the shift numbers S.sub.0 to S.sub.6 is selected in turn and assigned to each level, beginning with the maximum level to 1/2 thereof, shift number S.sub.0 is assigned, from 1/2 to 1/4, shift number S.sub.1, and so on. If two levels corresponding to the shift numbers S.sub.0 and S.sub.1 are compared, although the output of mantissa DAC 6 has the same range in both cases, the output of the exponent DAC 9 is half the level corresponding to the shift number S.sub.1 as in the shift number S.sub.0.
If both the mantissa DAC 6 and exponent DAC 9 had 16-bit accuracy (i.e., (100 * 2.sup.-16)%), the relationship between the analog output level of the sinusoidal wave and the total harmonic distortion (called "distortion" for brevity hereafter) of the analog output level measured by a distortion meter, would be shown by solid line A in FIG. 4. First, line A shows saw-tooth variation, because every time the shift number is incremented by 1 the amplitude of the mantissa increases by 6 dB over that just immediately prior to the shift, and thus distortion decreases by 6 dB each time the shift number is changed. Second, the average level of the line A is kept constant. This is because error E applied from the mantissa DAC 6 to the input terminal of the R-2R ladder network 10 of the exponent DAC 9 is halved each time the shift number changes from S.sub.0 to S.sub.6, such as 2.sup.-1 .multidot.E, 2.sup.-2 .multidot.E, . . . , 2.sup.-6 .multidot.E, and hence error E and the level of analog output are simultaneously halved. Thus, average distortion of the analog signal is kept constant as long as the shift number is changed. Consequently, distortion of the analog signal varies between two levels (between 0.00125% and 0.0025%, for example) in the range from 0 to 36 dB in which the shift number is altered, whereas distortion in the smaller range is inversely proportional to the level of analog output V.sub.OUT because the shift number is not changed.
As described above, if both mantissa DAC 6 and exponent DAC 9 have 16-bit accuracy, a low level distortion is obtained as shown by solid line A in FIG. 4. In practice, however, a low level distortion cannot be achieved because 16-bit accuracy of exponent DAC 9 cannot be obtained. More specifically, though 14-bit to 16-bit accuracy can be achieved for the mantissa DAC 6 by trimming or other means to compensate for errors of each resistor in the R-2R ladder network 8, it is very difficult to obtain similar accuracy for exponent DAC 9. This is because the resistor of ladder network 10 in exponent DAC 9 are connected to form an integral part, and so each resistance there of cannot be measured separately and hence the trimming thereof is difficult. In particular, it is very difficult to achieve high accuracy in a range where the level of analog output is small. Consequently, sufficient adjustment of resistors in the exponent DAC 9 is practically impossible, so the actual accuracy obtained is about 10- to 12-bits.
For this reason, even if mantissa DAC 6 of 16-bit accuracy is employed, the accuracy of the resulting output from exponent DAC 9 is only about 10- to 12-bits, as shown by broken line B in FIG. 4. First, the distortion in this case shows saw-tooth variation, because every time the shift number is incremented by one, the weight of exponent DAC 9 is decreased by 6 dB while the amplitude of the mantissa increases by 6 dB over that just immediately prior to the shift, and thus distortion decreases significantly from 10- to 12-bit accuracy. Second, the distortion is improved to 0.00125% abruptly at -36 dB because the shift number S.sub.6 which is used thereunder is free from the low accuracy of exponent DAC 9.
The fact that distortion increases near the maximum output (0 dB), causes a critical problem in digital audio apparatus such as compact disk players, because performance of these apparatus is specified by distortion at 0 dB output.